Design of reversible multiplexer/de-multiplexer
© 2014 IEEE. Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, fo...
| Main Authors: | , , , |
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| Format: | Conference Paper |
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Institute of Electrical and Electronics Engineers Inc.
2014
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| Online Access: | http://hdl.handle.net/20.500.11937/19685 |
| _version_ | 1848750101421359104 |
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| author | Gopal, Lenin Raj, N. Gopalai, A. Singh, A. |
| author_facet | Gopal, Lenin Raj, N. Gopalai, A. Singh, A. |
| author_sort | Gopal, Lenin |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | © 2014 IEEE. Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic logical functions such as AND, XOR, MUX etc. Besides these functions, other advantage of the proposed R-I gate is that it can be used as a 1/2 de-multiplexer without requiring any extra logic circuits and the proposed R-II gate can be used as a half adder circuit. The proposed reversible gates are implemented and verified using Xilinx ISE 10.1 software. The simulation results show that the proposed designs are more efficient in terms of gate count, garbage outputs and constant inputs than the existing reversible logic gate. |
| first_indexed | 2025-11-14T07:31:29Z |
| format | Conference Paper |
| id | curtin-20.500.11937-19685 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T07:31:29Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers Inc. |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-196852017-09-13T13:49:38Z Design of reversible multiplexer/de-multiplexer Gopal, Lenin Raj, N. Gopalai, A. Singh, A. © 2014 IEEE. Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic logical functions such as AND, XOR, MUX etc. Besides these functions, other advantage of the proposed R-I gate is that it can be used as a 1/2 de-multiplexer without requiring any extra logic circuits and the proposed R-II gate can be used as a half adder circuit. The proposed reversible gates are implemented and verified using Xilinx ISE 10.1 software. The simulation results show that the proposed designs are more efficient in terms of gate count, garbage outputs and constant inputs than the existing reversible logic gate. 2014 Conference Paper http://hdl.handle.net/20.500.11937/19685 10.1109/ICCSCE.2014.7072755 Institute of Electrical and Electronics Engineers Inc. restricted |
| spellingShingle | Gopal, Lenin Raj, N. Gopalai, A. Singh, A. Design of reversible multiplexer/de-multiplexer |
| title | Design of reversible multiplexer/de-multiplexer |
| title_full | Design of reversible multiplexer/de-multiplexer |
| title_fullStr | Design of reversible multiplexer/de-multiplexer |
| title_full_unstemmed | Design of reversible multiplexer/de-multiplexer |
| title_short | Design of reversible multiplexer/de-multiplexer |
| title_sort | design of reversible multiplexer/de-multiplexer |
| url | http://hdl.handle.net/20.500.11937/19685 |