Design and synthesis of reversible arithmetic and Logic Unit (ALU)
In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of rever...
| Main Authors: | , , , , |
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| Format: | Conference Paper |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2014
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| Online Access: | http://hdl.handle.net/20.500.11937/14507 |
| _version_ | 1848748641055932416 |
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| author | Gopal, Lenin Mohd Mahayadin, N. Chowdhury, A. Gopalai, A. Singh, A. |
| author_facet | Gopal, Lenin Mohd Mahayadin, N. Chowdhury, A. Gopalai, A. Singh, A. |
| author_sort | Gopal, Lenin |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design. |
| first_indexed | 2025-11-14T07:08:16Z |
| format | Conference Paper |
| id | curtin-20.500.11937-14507 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T07:08:16Z |
| publishDate | 2014 |
| publisher | Institute of Electrical and Electronics Engineers Inc. |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-145072017-09-13T14:06:28Z Design and synthesis of reversible arithmetic and Logic Unit (ALU) Gopal, Lenin Mohd Mahayadin, N. Chowdhury, A. Gopalai, A. Singh, A. In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design. 2014 Conference Paper http://hdl.handle.net/20.500.11937/14507 10.1109/I4CT.2014.6914191 Institute of Electrical and Electronics Engineers Inc. restricted |
| spellingShingle | Gopal, Lenin Mohd Mahayadin, N. Chowdhury, A. Gopalai, A. Singh, A. Design and synthesis of reversible arithmetic and Logic Unit (ALU) |
| title | Design and synthesis of reversible arithmetic and Logic Unit (ALU) |
| title_full | Design and synthesis of reversible arithmetic and Logic Unit (ALU) |
| title_fullStr | Design and synthesis of reversible arithmetic and Logic Unit (ALU) |
| title_full_unstemmed | Design and synthesis of reversible arithmetic and Logic Unit (ALU) |
| title_short | Design and synthesis of reversible arithmetic and Logic Unit (ALU) |
| title_sort | design and synthesis of reversible arithmetic and logic unit (alu) |
| url | http://hdl.handle.net/20.500.11937/14507 |