FPGA implementation of wideband IQ imbalance correction in OFDM receivers
This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented on a Xilinx Virtex-4 field programmable gate array (FPGA). The flexible architectu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Conference Paper |
| Published: |
IEEE eXpress Conference Publishing
2008
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| Online Access: | http://hdl.handle.net/20.500.11937/12595 |
| _version_ | 1848748117637201920 |
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| author | Palipana, Rajitha Chung, Kah-Seng |
| author2 | ICCSC 2008 Technical Program Committee |
| author_facet | ICCSC 2008 Technical Program Committee Palipana, Rajitha Chung, Kah-Seng |
| author_sort | Palipana, Rajitha |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented on a Xilinx Virtex-4 field programmable gate array (FPGA). The flexible architecture of the implementation makes it readily adaptable for different broadband applications, such as DVB-T/H, WLAN, and WiMAX. The proposed correction scheme is resilient against multipath fading and frequency offset. When applied to DVB-T, it is shown that an 11-bit arithmetic precision is sufficient to achieve the required BER of 2x10-4 at an SNR of 16.5 dB. Using this bit-precision, the implementation consumes 1686 Virtex-4 slices equivalent to about 42600 gates. |
| first_indexed | 2025-11-14T06:59:57Z |
| format | Conference Paper |
| id | curtin-20.500.11937-12595 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T06:59:57Z |
| publishDate | 2008 |
| publisher | IEEE eXpress Conference Publishing |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-125952017-09-13T16:01:59Z FPGA implementation of wideband IQ imbalance correction in OFDM receivers Palipana, Rajitha Chung, Kah-Seng ICCSC 2008 Technical Program Committee This paper describes the implementation of a digital compensation scheme, called CSAD, for correcting the effects of wideband gain and phase imbalances in dual-branch OFDM receivers. The proposed scheme is implemented on a Xilinx Virtex-4 field programmable gate array (FPGA). The flexible architecture of the implementation makes it readily adaptable for different broadband applications, such as DVB-T/H, WLAN, and WiMAX. The proposed correction scheme is resilient against multipath fading and frequency offset. When applied to DVB-T, it is shown that an 11-bit arithmetic precision is sufficient to achieve the required BER of 2x10-4 at an SNR of 16.5 dB. Using this bit-precision, the implementation consumes 1686 Virtex-4 slices equivalent to about 42600 gates. 2008 Conference Paper http://hdl.handle.net/20.500.11937/12595 10.1109/ICCSC.2008.146 IEEE eXpress Conference Publishing fulltext |
| spellingShingle | Palipana, Rajitha Chung, Kah-Seng FPGA implementation of wideband IQ imbalance correction in OFDM receivers |
| title | FPGA implementation of wideband IQ imbalance correction in OFDM receivers |
| title_full | FPGA implementation of wideband IQ imbalance correction in OFDM receivers |
| title_fullStr | FPGA implementation of wideband IQ imbalance correction in OFDM receivers |
| title_full_unstemmed | FPGA implementation of wideband IQ imbalance correction in OFDM receivers |
| title_short | FPGA implementation of wideband IQ imbalance correction in OFDM receivers |
| title_sort | fpga implementation of wideband iq imbalance correction in ofdm receivers |
| url | http://hdl.handle.net/20.500.11937/12595 |