Search Results - Pradhan, D.K.

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    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) by Singh, Ashutosh Kumar, Bera, A., Rahaman, H., Mathew, J., Pradhan, D.k.

    Published 2009
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  2. 2
    A Galois field-based logic synthesis with testability

    A Galois field-based logic synthesis with testability by Mathew, J., Jabir, A.M., Singh, Ashutosh Kumar, Rahaman, H., Pradhan, D.K.

    Published 2010
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